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25AA080/25LC080/25C080
3.6
Write Status Register ( WRSR )
TABLE 3-2:
ARRAY PROTECTION
The Write Status Register ( WRSR ) instruction allows the
user to select one of four levels of protection for the
array by writing to the appropriate bits in the Status reg-
ister. The array is divided up into four segments. The
user has the ability to write-protect none, one, two, or
all four of the segments of the array. The partitioning is
controlled as shown in Table 3-2.
The Write-Protect Enable (WPEN) bit is a nonvolatile
bit that is available as an enable bit for the WP pin. The
Write-Protect (WP) pin and the Write-Protect Enable
BP1
0
0
1
1
BP0
0
1
0
1
Array Addresses
Write-Protected
none
upper 1/4
(0300h - 03FFh)
upper 1/2
(0200h - 03FFh)
all
(0000h - 03FFh)
(WPEN) bit in the Status register control the program-
mable hardware write-protect feature. Hardware write
protection is enabled when WP pin is low and the
WPEN bit is high. Hardware write protection is disabled
when either the WP pin is high or the WPEN bit is low.
When the chip is hardware write-protected, only writes
to nonvolatile bits in the Status register are disabled.
See Table 3-3 for a matrix of functionality on the WPEN
bit.
See Figure 3-5 for the WRSR timing sequence.
FIGURE 3-7:
CS
WRITE STATUS REGISTER TIMING SEQUENCE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
instruction
data to Status register
SI
0
0
0
0
0
0
0
1
7
6
5
4
3
2
1
0
High-impedance
SO
? 2004 Microchip Technology Inc.
DS21230D-page 11
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